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Design Preparation Instructions

Overview
A circuit design must conform to specific constraints in order to be tested using the SEU simulator. The Simulator requires that the design be duplicated. One copy will be the "golden" circuit, allowed to operate normally. The other copy will be the design under test, into which the Simulator will inject single bit upsets in the configuration bitstream. Physically, the design will be placed with the copy under test in pe1 (processing element 1) and the golden copy in pe2 (see figure 1 below). The outputs of pe1 are on the LEFT pads. The outputs of pe2 are on the RIGHT pads. If the design is carefully prepared with specific names for the input and output ports (given below), it can be synthesized to create two different .bit files which are mapped to the correct pads.

Circuit Design
  1. Use this VHDL template as a starting point for the top level of the circuit design.
  2. Create a design using VHDL with the following constraints
    • Inputs
      • The input to the circuit must be named XP_IN.
        • 72 bits are alloted to XP_IN.
        • To use less than 72 bits, comment out the unwanted nets in both .ucf files.
    • Outputs
      • The output of the circuit must be named XP_OUT.
        • 72 bits are alloted to XP_OUT.
        • To use less than 72 bits, comment out the unwanted nets in both .ucf files.
      • All 'state' of the design to be compared against the "golden" copy must be mapped to outputs of the circuit.
    • Clock
      • The clock must be named XP_PCLK.
      • XP_PCLK must be buffered with an IBUFG followed by a BUFG
      • No more than one clock is allowed
    • Reset
      • There must be a port named XP_RST (width 1) which will be used for global reset by the simulator.
      • XP_RST must be buffered with an IBUFG, latched in a flip-flop and then buffered through a BUFG
      • All 'state' of the design must have XP_RST hooked to it. (Use the buffered copy of XP_RST - see above line)
      • User defined resets to the circut must be inputs through XP_IN. (The GSR signal is used to control SEU simulation.)
      • OR together with XP_RST (the buffered copy - see above) any user defined resets the design may have.
      • A special constraint must be included in each .ucf file:
            INST "RST_BUFG" LOC = GCLKBUF0;
        where RST_BUFG is the instance name of XP_RST's BUFG
    • Other
      • LUT RAMs or SRL16s are not allowed in the design.
Design Synthesis
  • Create an edif file of the design.
  • Synthesize the circuit using these instructions
  • A step by step tutorial of this entire process can be found here.

Figure 1:
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