As mentioned in the previous section on design preparation, the circuit will be placed with the copy under test in pe1 (processing element 1) and the golden copy in pe2 (see figure 1 below). The outputs of pe1 are on the LEFT pads. The outputs of pe2 are on the RIGHT pads. To map the circuit to the correct pads, the design must be synthesized twice using different .ucf files in order to map the outputs to the correct pads. (The inputs of both pe1 and pe2 are on the XBAR pads.) This process is quite easy if the input and output ports are labeled with the specific names given below and the design is synthesized using the provided .ucf files below.

1. Create a xp1 directory and a xp2 directory
2. Create the Placed & Routed .ncd files (using the Xilinx XST 5.1 tools)
• Copy the edif file to both the xp1 and xp2 directories
• Repeat the following steps in both directories (replacing xp1 with xp2 when in the xp2 directory)
1. edif2ngd xp1.edf
2. ngdbuild xp1 -p v1000fg680-6 -uc xp1.ucf
3. map xp1
4. par -w -ol 5 xp1.ncd xp1.par.ncd
3. Convert the .ncd files for xp1 to .xdl format
• Before the SEU simulation tests can be performed, half-latches must be removed from the design to be placed in xp1.
• BYU will remove the half-latches, but the required file format is .xdl
• To convert the Placed and Routed .ncd file for xp1 to .xdl format use the xdl tool. At the command line type: xdl -ncd2xdl xp1.par.ncd xp1.xdl
4. Send the .xdl file to BYU for half-latch removal
• Currently Keith Morgan is in charge of SEU simulations. Please send the .xdl file to him at this e-mail address: bhp7@et.byu.edu
• BYU will send back a xp1-fixed.xdl file
5. Convert the fixed .xdl file back to .ncd format
• At the command line type: xdl -xdl2ncd xp1-fixed.xdl xp1-fixed.ncd
6. Place and Route the fixed .ncd file for xp1
• The half-latch removal process disrupts the placement and routing.
• At the command line type: par -w -p xp1-fixed.ncd xp1-fixed.par.ncd
7. Create the .bit Files
• Set these environment variables
• XVKMA_CORE_LUT_PACK=TRUE
• GUIDE_NEW=TRUE
• Repeat the following step in both the xp1 and xp2 directories to create a .bit file for both xp1 and xp2 (using the Xilinx XST 5.1 tools) (replacing xp1-fixed with xp2 when in the xp2 directory)
1. bitgen -w -g StartupClk:Cclk -g readback -g persist:X8 -g DONE_cycle:6 xp1-fixed.par.ncd xp1-fixed.bit
8. Send the .bit files to BYU for SEU simulation.
• Currently Keith Morgan is in charge of SEU simulations. Please send the xp1-fixed.bit file and the xp2.bit file to him at this e-mail address: bhp7@et.byu.edu

• A step by step tutorial of the entire process can be found here.