library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; ------------------------------------------------------------------------------- -- New and improved X0 design for use with the SLAAC1-V SEU Simulator/Fault -- Injection Tool. -- -- New Features: -- input test vectors from memory!! No longer the need to use only LFSR input -- + 72 bits of memory data (uses two memory banks, 36 bits each) -- + 256K deep (18 address lines) -- ability to stop the clock from X0 -- + clock stops after user-indicated number of cycles -- + useful for guaranteeing that all of the desired test vectors have been -- presented to the design under test without the necessity of -- single-stepping the clock -- mask for output bits from design under test -- + removes false errors that occured before - only those bits indicated are -- compared against the golden design -- + useful for the case when fewer than 72 output pins are needed -- ?? TMR ?? -- ------------------------------------------------------------------------------- -- Control Registers -- -- Input: (from HOST) -- ------ -- 0. select which error stats register to write to register 0 -- + 0: number of errors observed thus far -- + 1: number of cycles since the first error was observed -- + 2: number of cycles since the most recently observed error -- 1. select which portion of input/output data to write to register 1 -- + 0x0: test vector out [31:0] -- + 0x1: test vector out [63:32] -- + 0x2: test vector out [71:64] for lower order bits - zero extended -- + 0x3: X1 datain [31:0] -- + 0x4: X1 datain [63:32] -- + 0x5: X1 datain [71:64] - zero extended -- + 0x6: X2 datain [31:0] -- + 0x7: X2 datain [63:32] -- + 0x8: X2 datain [71:64] - zero extended -- 2. run-cycles per iteration -- 3. test vector data mask (lower 32 bits) -- 4. test vector data mask (upper 32 bits) -- 5. output data mask (lower 32 bits) -- 6. output data mask (upper 32 bits) -- 7. select which data to send to X1/X2 (LFSR data or memory data) -- -- *OR* -- -- Have Register 0 be a control register containing a command to execute. -- When this register contains zero, nothing will happen. As long as we single -- step to clock (only necessary when initializing), we can have a different -- command word for each instruction, and use the remaining registers for -- input. Personally, I think this approach is the best. -- -- -- -- Output: (to HOST) -- ------- -- 0. error stats -- 1. input/output data -- 2. -- 3. -- 4. -- 5. -- 6. -- 7. -- ------------------------------------------------------------------------------- -- Author: Eric Johnson - dej23 'at' ee.byu.edu -- (c) 2004 Brigham Young University -- ------------------------------------------------------------------------------- entity x0v_part is generic ( NODE_ID : integer := 0; PE_ID : integer := 0); port ( X0_CLK : in std_logic; X0_RESET : in std_logic; X0_HALT : out std_logic; X0_LEFT : inout std_logic_vector(71 downto 0); X0_RIGHT : inout std_logic_vector(71 downto 0); X0_XBAR : inout std_logic_vector(71 downto 0); X0_FIFOA0_DATA : in std_logic_vector(63 downto 0); X0_FIFOA0_TAG : in std_logic_vector(3 downto 0); X0_FIFOA0_EMPTY : in std_logic; X0_FIFOA0_RE : out std_logic; X0_FIFOA1_DATA : in std_logic_vector(63 downto 0); X0_FIFOA1_EMPTY : in std_logic; X0_FIFOA1_RE : out std_logic; X0_FIFOB0_DATA : out std_logic_vector(63 downto 0); X0_FIFOB0_TAG : out std_logic_vector(3 downto 0); X0_FIFOB0_WE : out std_logic; X0_FIFOB0_FULL : in std_logic; X0_FIFOB1_DATA : out std_logic_vector(63 downto 0); X0_FIFOB1_WE : out std_logic; X0_FIFOB1_FULL : in std_logic; X0_MEM0_ADDR : out std_logic_vector(18 downto 0); X0_MEM0_DIN : in std_logic_vector(35 downto 0); X0_MEM0_DIN_VLD: in std_logic; X0_MEM0_DOUT : out std_logic_vector(35 downto 0); X0_MEM0_WE_N : out std_logic; X0_MEM0_CE_N : out std_logic; X0_MEM0_LD_N : out std_logic; X0_MEM0_SEL : out std_logic_vector(2 downto 0); X0_MEM0_OVERRIDE: in std_logic; X0_MEM0_BUSY : in std_logic; X0_MEM1_ADDR : out std_logic_vector(18 downto 0); X0_MEM1_DIN : in std_logic_vector(35 downto 0); X0_MEM1_DIN_VLD: in std_logic; X0_MEM1_DOUT : out std_logic_vector(35 downto 0); X0_MEM1_WE_N : out std_logic; X0_MEM1_CE_N : out std_logic; X0_MEM1_LD_N : out std_logic; X0_MEM1_SEL : out std_logic_vector(2 downto 0); X0_MEM1_OVERRIDE: in std_logic; X0_MEM1_BUSY : in std_logic; X0_MEM_MODE : in std_logic; X0_MEM_PREEMPT : in std_logic; X0_HDSKIF : inout std_logic_vector(2 downto 0); X0_HDSKX1 : inout std_logic_vector(1 downto 0); X0_HDSKX2 : inout std_logic_vector(1 downto 0); X0_CTRL_READ_DATA : inout std_logic_vector(31 downto 0) := (others => 'Z'); X0_CTRL_WRITE_DATA: in std_logic_vector(31 downto 0); X0_CTRL_WE : in std_logic_vector(7 downto 0); X0_CTRL_OE : in std_logic_vector(7 downto 0); X0_CTRL_WCLK : in std_logic; X0_IO_SEL : out std_logic_vector(1 downto 0); X0_LED : out std_logic_vector(1 downto 0) ); end x0v_part; architecture example of x0v_part is signal dout : std_logic_vector(63 downto 0); signal tout : std_logic_vector(3 downto 0); signal empty_d : std_logic; begin -- speedfreak -- Just loop the data from FIFOA0 to FIFOB0. Don't worry about the -- FIFOB0_FULL flag, assume that the host will read every word OK. process(X0_RESET, X0_CLK) begin if (X0_RESET = '1') then empty_d <= '1'; X0_FIFOB0_WE <= '0'; dout <= (others => '0'); tout <= (others => '0'); X0_FIFOB0_DATA <= (others => '0'); X0_FIFOB0_TAG <= (others => '0'); X0_FIFOA0_RE <= '0'; elsif X0_CLK'event and X0_CLK = '1' then X0_FIFOA0_RE <= '1'; empty_d <= X0_FIFOA0_EMPTY; X0_FIFOB0_WE <= not(empty_d); dout <= X0_FIFOA0_DATA; tout <= X0_FIFOA0_TAG; X0_FIFOB0_DATA <= dout; X0_FIFOB0_TAG <= tout; end if; end process; -- tristate chip to chip connections X0_LEFT <= (others => 'Z'); X0_RIGHT <= (others => 'Z'); X0_XBAR <= (others => 'Z'); -- disable FIFOA1/B1 ports X0_FIFOA1_RE <= '0'; X0_FIFOB1_DATA <= (others => 'Z'); X0_FIFOB1_WE <= '0'; -- disable MEM0 X0_MEM0_DOUT <= (others => 'Z'); X0_MEM0_ADDR <= (others => 'Z'); X0_MEM0_WE_N <= '1'; X0_MEM0_CE_N <= '1'; X0_MEM0_LD_N <= '0'; X0_MEM0_SEL <= "000"; -- disable MEM1 X0_MEM1_DOUT <= (others => 'Z'); X0_MEM1_ADDR <= (others => 'Z'); X0_MEM1_WE_N <= '1'; X0_MEM1_CE_N <= '1'; X0_MEM1_LD_N <= '0'; X0_MEM1_SEL <= "000"; -- disable control ports X0_CTRL_READ_DATA <= (others => 'Z'); X0_IO_SEL <= "00"; X0_LED <= (others => 'Z'); end example;