-------------------------------------------------------------------
-- Top Level VHDL Template for logic designs to be used
-- in the SEU Simulator developed by Eric Johnson at BYU
--
-- Written by Keith Morgan
-- Brigham Young University
-- Configurable Computing Lab
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
  Port (
    -- main board i/o
    XP_PCLK     : in std_logic;
    XP_RST      : in std_logic;
    XP_IN       : in std_logic_vector(71 downto 0);
    XP_OUT      : out std_logic_vector(71 downto 0)
  );
end top;

architecture Behavioral of top is

  component IBUFG
    port (I: in STD_LOGIC;
          O: out STD_LOGIC);
  end component; 

  component BUFG
    port (I: in STD_LOGIC;
          O: out STD_LOGIC);
  end component; 

  signal clk_buf : std_logic;
  signal clk : std_logic;
  signal rst_in : std_logic;
  signal rst_buf : std_logic;
  signal rst : std_logic;
  
begin

  -- clk needs to be mapped to the global clock network
  -- First it is buffered through ibufg followed by a bufg.
  CLK_IBUFG : IBUFG
    port map(I => XP_PCLK, O => clk_buf);

  CLK_BUFG : BUFG port map (
    I => clk_buf,
    O => clk);
  
  -- Buffer XP_RST with an IBUFG because
  -- XP_RST comes in through a glck pin
  -- on the SLAAC1V Board
  RST_IBUFG : IBUFG port map (
    I => XP_RST,
    O => rst_in);

  -- Try and account for the board
  -- skew on XP_RST by latching
  -- the signal (rst_in) in a flip-flop
  -- immediately.
  reset_in: process (clk)
  begin  -- process reset_in
    if clk'event and clk = '1' then  -- rising clock edge
      rst_buf <= rst_in;
    end if;
  end process reset_in;

  -- The BUFG distributes rst on the
  -- global network.
  RST_BUFG : BUFG port map (
    I => rst_buf,
    O => rst);

  -- Add Design Here
 
end Behavioral;