library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

-------------------------------------------------------------------------------
-- Example x0v_part design.  In this design, we simply loop the FIFOA0 data
-- back out through FIFOB0.
-------------------------------------------------------------------------------


entity x0v_part is

  generic (
    NODE_ID : integer := 0;
    PE_ID   : integer := 0);

  port (
	  X0_CLK         : in    std_logic;
	  X0_RESET       : in    std_logic;
	  X0_HALT        : out   std_logic;
	  X0_LEFT        : inout std_logic_vector(71 downto 0);
	  X0_RIGHT       : inout std_logic_vector(71 downto 0);
	  X0_XBAR        : inout std_logic_vector(71 downto 0);
	  X0_FIFOA0_DATA  : in    std_logic_vector(63 downto 0);
	  X0_FIFOA0_TAG   : in    std_logic_vector(3 downto 0);
	  X0_FIFOA0_EMPTY : in    std_logic;
	  X0_FIFOA0_RE    : out   std_logic;
	  X0_FIFOA1_DATA  : in    std_logic_vector(63 downto 0);
	  X0_FIFOA1_EMPTY : in    std_logic;
	  X0_FIFOA1_RE    : out   std_logic;
	  X0_FIFOB0_DATA  : out   std_logic_vector(63 downto 0);
	  X0_FIFOB0_TAG   : out   std_logic_vector(3 downto 0);
	  X0_FIFOB0_WE    : out   std_logic;
	  X0_FIFOB0_FULL  : in    std_logic;
	  X0_FIFOB1_DATA  : out   std_logic_vector(63 downto 0);
	  X0_FIFOB1_WE    : out   std_logic;
	  X0_FIFOB1_FULL  : in    std_logic;
	  X0_MEM0_ADDR   : out   std_logic_vector(18 downto 0);
	  X0_MEM0_DIN    : in    std_logic_vector(35 downto 0);
	  X0_MEM0_DIN_VLD: in    std_logic;
	  X0_MEM0_DOUT   : out   std_logic_vector(35 downto 0);
	  X0_MEM0_WE_N   : out   std_logic;
	  X0_MEM0_CE_N   : out   std_logic;
	  X0_MEM0_LD_N   : out   std_logic;
	  X0_MEM0_SEL    : out   std_logic_vector(2 downto 0);
	  X0_MEM0_OVERRIDE: in    std_logic;
	  X0_MEM0_BUSY   : in    std_logic;
	  X0_MEM1_ADDR   : out   std_logic_vector(18 downto 0);
	  X0_MEM1_DIN    : in	 std_logic_vector(35 downto 0);
	  X0_MEM1_DIN_VLD: in    std_logic;
	  X0_MEM1_DOUT   : out	 std_logic_vector(35 downto 0);
	  X0_MEM1_WE_N   : out   std_logic;
	  X0_MEM1_CE_N   : out   std_logic;
	  X0_MEM1_LD_N   : out   std_logic;
	  X0_MEM1_SEL    : out   std_logic_vector(2 downto 0);
	  X0_MEM1_OVERRIDE: in    std_logic;
	  X0_MEM1_BUSY   : in    std_logic;

          X0_MEM_MODE    : in    std_logic;
          X0_MEM_PREEMPT : in    std_logic;
	  X0_HDSKIF      : inout std_logic_vector(2 downto 0);
	  X0_HDSKX1      : inout std_logic_vector(1 downto 0);
	  X0_HDSKX2      : inout std_logic_vector(1 downto 0);
	  X0_CTRL_READ_DATA : inout std_logic_vector(31 downto 0) := (others => 'Z');
	  X0_CTRL_WRITE_DATA: in    std_logic_vector(31 downto 0);
	  X0_CTRL_WE        : in    std_logic_vector(7 downto 0);
	  X0_CTRL_OE        : in    std_logic_vector(7 downto 0);
	  X0_CTRL_WCLK	    : in    std_logic;
	  X0_IO_SEL	 : out   std_logic_vector(1 downto 0);
	  X0_LED         : out   std_logic_vector(1 downto 0)
	  );
end x0v_part;


architecture example of x0v_part is
    signal dout : std_logic_vector(63 downto 0);
    signal tout : std_logic_vector(3 downto 0);
    signal empty_d : std_logic;

begin  -- speedfreak
    -- Just loop the data from FIFOA0 to FIFOB0.  Don't worry about the
    -- FIFOB0_FULL flag, assume that the host will read every word OK.
    process(X0_RESET, X0_CLK)
    begin
	if (X0_RESET = '1') then
	    empty_d <= '1';
	    X0_FIFOB0_WE <= '0';
	    dout <= (others => '0');
	    tout <= (others => '0');
	    X0_FIFOB0_DATA <= (others => '0');
	    X0_FIFOB0_TAG <= (others => '0');
	    X0_FIFOA0_RE <= '0';
	elsif X0_CLK'event and X0_CLK = '1' then
	    X0_FIFOA0_RE <= '1';
	    empty_d <= X0_FIFOA0_EMPTY;
	    X0_FIFOB0_WE <= not(empty_d);
	    dout <= X0_FIFOA0_DATA;
	    tout <= X0_FIFOA0_TAG;

	    X0_FIFOB0_DATA <= dout;
	    X0_FIFOB0_TAG <= tout;
	end if;
    end process;
    

    -- tristate chip to chip connections
    X0_LEFT   <= (others => 'Z');
    X0_RIGHT  <= (others => 'Z');
    X0_XBAR   <= (others => 'Z');
    
    -- disable FIFOA1/B1 ports
    X0_FIFOA1_RE   <= '0';
    X0_FIFOB1_DATA <= (others => 'Z');
    X0_FIFOB1_WE   <= '0';

    -- disable MEM0
    X0_MEM0_DOUT <= (others => 'Z');
    X0_MEM0_ADDR <= (others => 'Z');
    X0_MEM0_WE_N <= '1';
    X0_MEM0_CE_N <= '1';
    X0_MEM0_LD_N <= '0';
    X0_MEM0_SEL <= "000";

    -- disable MEM1
    X0_MEM1_DOUT <= (others => 'Z');
    X0_MEM1_ADDR <= (others => 'Z');
    X0_MEM1_WE_N <= '1';
    X0_MEM1_CE_N <= '1';
    X0_MEM1_LD_N <= '0';
    X0_MEM1_SEL <= "000";

    -- disable control ports
    X0_CTRL_READ_DATA <= (others => 'Z');
    X0_IO_SEL <= "00";
    X0_LED <= (others => 'Z');

end example;