# This is a sample Synplify project for synthesizing x0 in batch mode.  
# You should probably copy this file to each new project directory 
# because Synplicity is dumb and always sets the current directory to be
# the one that contains the script file, so you can't do something 
# clever like "synplify $SLAAC_ROOT/synth/x0_batch.prj" because a)  all 
# output files get dumped to $SLAAC_ROOT, and b) it looks in $SLAAC_ROOT 
# for all project files without an absolute path.  * HOWEVER * you can 
# achieve the same effect by doing this:
# 
# 1.  Compile with a makefile.  In the makefile, copy this file to the 
#     local project directory before running synplify.
#
# 2.  Create the file "x0_files.tcl".  In this file list all the 
#     project-specific files, listed as "add_file -vhdl ..." in normal 
#     Synplify-project syntax.
#   -- OR -- 
#     Confine all your project-specific code to a file named "x0.vhd", 
#
# 3.  Run the makefile - this script will automatically look for
#     "x0_files.tcl" and source it if it exists.  If not, by default it
#     tries to include the file "x0.vhd".
#
# Either approach will let you compile all your designs without ever 
# modifying this project file.

# Make sure that you set these two variables correctly.
set SLAAC_ROOT "/usr/local/slaac1v"
set SYNPLIFY_ROOT "/cad/synplify_75"

#-- Synplicity, Inc.
#-- Synplify version 5.3.1
#-- Project file E:\slaac1v\fpga\if\syn\slaac1v_ifx0.prj
#-- Written on Tue Mar 28 16:07:45 2000

#device options
set_option -technology Virtex
set_option -part XCV1000
set_option -package FG680
set_option -speed_grade -6

# Add the user design.  Synplicity needs Virtex-specific attributes on 
# Xilinx components.
add_file -vhdl -lib work "$SYNPLIFY_ROOT/lib/xilinx/virtex.vhd"

if {[file exists "x0_files.tcl"]} {
    source "x0_files.tcl"
} else {
    add_file -vhdl -lib work "x0.vhd"
}

# Now compile all the PCI bridge files
add_file -vhdl -lib work "$SLAAC_ROOT/sim/UserMemoryPort.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/bridge_package.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/dma_package.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/cross_counter.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/compare.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/graycount_rd_sp.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/graycount_rd.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/graycount_sp.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/graycount.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/fifo_control_rd_sp.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/fifo_control_rd.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMA_State_Machine.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMAPrefetch.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMAInputControl.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMAOutputControl.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMAInputFifo.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMAOutputFifo.vhd" 
#add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/DMA_Top.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/cross_clock_pulse.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/clock_synth_mod.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/edge_catcher.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/down_counter.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/xn_ctrl_mod.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/revision_reg.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/pciclk_divider.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/interrupt.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/handshake.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/MailboxInputFifo.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/MailboxOutputFifo.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/decode.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/MemoryReadFifo.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/MemoryWriteFifo.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/BufferedMemoryPort.vhd" 
#add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/dma_memory_port.vhd" 
#add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/dma_memory_module.vhd" 
#add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/memory_module.vhd" 
#add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/dma_log_memmod.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/PCI_Slave_State_Machine.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/mclk_pci_skew_control.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/xvpi_interface.vhd" 
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/bus_logger.vhd"
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/slaac1v_pci_bridge.vhd" 

# Compile the PCI core wrappers
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_core/cfg.vhd"
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_core/pcim_lc.vhd"

# Now compile the top level, and we're done.
add_file -constraint "$SLAAC_ROOT/synth/slaac1v_ifx0.sdc"
add_file -vhdl -lib work "$SLAAC_ROOT/synth/pci_bridge/slaac1v_ifx0.vhd"


#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
set_option -resource_sharing true

#map options
set_option -frequency 33.000
set_option -fanout_limit 100
set_option -maxfan_hard false
set_option -disable_io_insertion false

#simulation options
set_option -write_verilog false
set_option -write_vhdl false

#automatic place and route (vendor) options
set_option -write_apr_constraint true

#MTI Cross Probe options
#set_option -mti_root ""

#set result format/file last
project -result_file "x0.edf"