-------------------------------------------------------------------
-- Top Level Logic for xp_tutorial circuit
--
-- Written by Keith Morgan
-- Brigham Young University
-- Configurable Computing Lab
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity top is
  Port (
    -- main board i/o
    XP_PCLK     : in std_logic;
    XP_RST      : in std_logic;
    XP_IN       : in std_logic_vector(71 downto 0);
    XP_OUT      : out std_logic_vector(71 downto 0)
  );
end top;

architecture Behavioral of top is

  component IBUFG
    port (I: in STD_LOGIC;
          O: out STD_LOGIC);
  end component; 

  component BUFG
    port (I: in STD_LOGIC;
          O: out STD_LOGIC);
  end component; 

  signal clk_buf : std_logic;
  signal clk : std_logic;
  signal rst_in : std_logic;
  signal rst_buf : std_logic;
  signal rst : std_logic;
  signal en : std_logic := '1';
  signal input_a : std_logic_vector(35 downto 0) := (others => '0');
  signal input_b : std_logic_vector(35 downto 0) := (others => '0');
  signal adder_out : std_logic_vector(35 downto 0);
  signal subtractor_out : std_logic_vector(35 downto 0);
  signal concat_out : std_logic_vector(71 downto 0);
  
  
begin

  --clk needs to be mapped to the global clock network
  --First it is buffered through ibufg and then through bufg
  --clk <= XP_PCLK;
  CLK_IBUFG : IBUFG port map (
    I => XP_PCLK,
    O => clk_buf);
  CLK_BUFG : BUFG port map (
    I => clk_buf,
    O => clk);

  -- Buffer XP_RST with an IBUFG because
  -- XP_RST comes in through a glck pin
  -- on the SLAAC1V Board
  RST_IBUFG: IBUFG port map (
    I => XP_RST,
    O => rst_in);

  -- Try and account for the board
  -- skew on XP_RST by latching
  -- the signal (rst_in) in a flip-flop
  -- immediately.
  reset_in: process (clk)
  begin  -- process reset_in
    if clk'event and clk = '1' then  -- rising clock edge
      rst_buf <= rst_in;
    end if;
  end process reset_in;

  -- The BUFG distributes rst on the
  -- global network.
  RST_BUFG : BUFG port map (
    I => rst_buf,
    O => rst);

  -- enable comes in through XP_IN[70]
  en <= XP_IN(70);
  -- input_a comes in through XP_IN[76:35]
  input_a <= '0' & XP_IN(69 downto 35);
  -- input_b comes in through XP_IN[34:0]
  input_b <= '0' & XP_IN(34 downto 0);
  -- XP_OUT comes through concat_out
  XP_OUT <= concat_out;
  
 -- purpose: This process takes input_a
 --          and adds it to input_b to
 --          create adder_out[35:0]
 -- type   : sequential
 -- inputs : clk, rst, en, input_a, input_b
 -- outputs: adder_out
adder: process (clk, rst)
 begin  -- process adder
   if rst = '1' then -- asynchronous reset (active high)
     adder_out <=  (others => '0');
   elsif clk'event and clk = '1' then  -- rising clock edge
     if en = '1' then
       adder_out <= input_a + input_b;
     end if;
   end if;
 end process adder; 

 -- purpose: This process takes input_a
 --          and subtracts input_b to
 --          create subtractor_out[35:0]
 -- type   : sequential
 -- inputs : clk, rst, en, input_a, input_b
 -- outputs: subtractor_out
subtractor: process (clk, rst)
 begin  -- process subtractor
   if rst = '1' then -- asynchronous reset (active high)
     subtractor_out <= (others => '0');
   elsif clk'event and clk = '1' then  -- rising clock edge
     if en = '1' then
       subtractor_out <= input_a - input_b;
     end if;
   end if;
 end process subtractor; 

-- purpose: This concatenates the outputs of the adder and subtractor.
-- type   : sequential
-- inputs : clk, rst, adder_out, subtractor_out
-- outputs: concat_out
concatenator: process (clk, rst)
begin  -- process concatenator
  if rst = '1' then -- asynchronous reset (active high)
    concat_out <= (others => '0');
  elsif clk'event and clk = '1' then  -- rising clock edge
    if en = '1' then
      concat_out(71 downto 36) <= adder_out;
      concat_out(35 downto 0) <= subtractor_out;
    end if;
  end if;
end process concatenator;
 
end Behavioral;