This project involves the development of an API for creating, modifying, or analyzing EDIF netlists within the Java programming language. We are currently using this API to analyze EDIF netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities.

The current release of our EDIF infrastructure includes the following tools:

• Java parser to parse pre-generated EDIF netlists
  
• JHDL generator for circuits represented in the EDIF data structure
  
• View EDIF circuit structure
• Simulate circuits (EDIF netlists based on Xilinx primitives)
• Integrate custom JHDL GUI tools
  
• EDIF merging routines for merging multiple-file EDIF circuits
• Primitive library for Xilinx FPGAs
  

Additional tools will be provided in future releases of the tool.