Package byucc.edif.libraries.xilinx

Parses the Xilinx unisim_VCOMP.vhd file, and generates an EdifLibrary containing Xilinx primitive cells

See:
Description

Interface Summary

Node
VhdlParserConstants
VhdlParserTreeConstants
VhdlParserVisitor

Class Summary

ASTabstract_literal
ASTarchitecture_body
ASTbound_expr
ASTcomp_decl
ASTdesign_file
ASTdirection
ASTentity_declaration
ASTfactor
ASTidentifier
ASTidentifier_list
ASTmode
ASTport_clause
ASTprocess_statement
ASTrange
ASTrelation
ASTshift_expression
ASTsignal_interface_decl
ASTsimple_expression
ASTsubtype
ASTterm
Edif2XilinxName	This class is used for converting hierarchical Edif names into valid flattened Xilinx names.
EdifXPowerCompare
EdifXPowerParser
ErrorHandler	Displays errors in syntax to std out.
InstanceHierarchy	This class represents an EdifCellInstance object within a hierarchy framework.
InstanceHierarchyIterator	This is an iterator class for the InstanceHierarchy object.
JHDL2XilinxNameMap	This class creates a Map object where the key of the Map is a JHDL Wire object.
JJTVhdlParserState
MultiNamedObject	When doing a compare on this object, it has multiple names, so the String passed-in for comparison will be compared against all of its names.
NetHierarchy
SignalSymbol	Represents and entry in the symbol tables for a signal or a variable.
SimpleCharStream	An implementation of interface CharStream, where the stream is assumed to contain only ASCII characters (without unicode processing).
SimpleNode	Represents a Node with a parent, children and an ID and is used by the parser.
Symbol	Represents a symbol--an entry in SymbolTable.
SymbolTable	Used for building the symbol tables.
Token	Describes the input token stream.
Vhdl	Opens a vhdl library, parses it, and creates a .java file that will create an EdifLibrary with all the cells located in the vhdl file converted to EdifCells.
Vhdl2JavaVisitor	This class will parse the xilinx primitive vhdl file (unisim_VCOMP.vhd) and generate a Java class that creates EdifCell objects for each instance in this library.
VhdlParser
VhdlParser.JJCalls
VhdlParserTokenManager
XilinxGenLib	This class is auto-generated - do not modify
XilinxLibrary	This class will create a Xilinx primitive library.
XilinxMacros	Inserts EdifCell primitives into the Xilinx Library that aren't already in the unisim_VCOMP.vhd file.
XilinxMergeParser	This is a simple class that contains a static method for parsing and merging edif files using the Xilinx library as the primitive library.

Exception Summary

ParseException

This exception is thrown when parse errors are encountered.

Error Summary

TokenMgrError
VhdlParser.LookaheadSuccess

Package byucc.edif.libraries.xilinx Description

Parses the Xilinx unisim_VCOMP.vhd file, and generates an EdifLibrary containing Xilinx primitive cells.

Related Links

• Xilinx Home Page
• Definition of Primitive
• VHDL-AMS Parser in JAVA

Package To Dos