edu.byu.ece.edif.arch.xilinx
Class Edif2XilinxName

java.lang.Object
  extended by edu.byu.ece.edif.arch.xilinx.Edif2XilinxName

public class Edif2XilinxName
extends java.lang.Object

This class is used for converting hierarchical EDIF names into valid flattened Xilinx names.

The rules for Xilinx Xpower names are as follows:

  1. Outputs For top-level "outputs" use the top-level instance names (old names) for instances having only one output that drive the output signal

    What about instances with multiple outputs?

  2. Signals
    1. Top-level signals: driven by ibufs/top-level instances:
      • use the top-level net name (old name) (not instance name)
    2. For names with hierarchy:
      1. find the highest level of hierarchy for the net
      2. find the hierarchy of this level. Add net name. (IE: if any of the net's portRefs refer to top level ports, don't add the port)
      3. append "old names" of each instance (separated by "/")
      4. append final net name
      5. Special case extension
        • driver & sinks are lower levels of hierarchy
  3. Logic
    1. Top-level and hierarchical names:
      1. find cell instance hierarchy
      2. append "old names" of each instance hierarchy level (separated by "/")
      3. Special case extensions
        • NOTE: "_rt" & ".WSGEN" specaial case extensions hacked
  4. Inputs
  5. IOs
Create a "Map" between:

Since:
Created on Jun 8, 2005
Author:
Nathan Rollins

Field Summary
protected  java.util.Map _innerNetsMapCache
           
protected  java.util.Map _nameObjectMap
          This is the main Map of the object.
protected  InstanceHierarchy _topInstHier
           
 
Constructor Summary
Edif2XilinxName(EdifCellInstance top)
           
Edif2XilinxName(InstanceHierarchy hier)
           
Edif2XilinxName(java.lang.String fileName)
           
 
Method Summary
 void createLogicMap(InstanceHierarchy hier)
           
 void createSignalMap(InstanceHierarchy hier)
           
 boolean drivesTopLevelOutputPort(NetHierarchy netHier)
           
static java.util.ArrayList getAllEdifNetNames(EdifNet net, InstanceHierarchy hier, NetHierarchy netHier, boolean includeTop)
           
 java.util.ArrayList getAllJHDLNetNames(NetHierarchy netHier, boolean includeTop)
           
static java.util.ArrayList getAllNetNames(EdifNet net, InstanceHierarchy hier, NetHierarchy netHier, boolean includeTop)
           
static java.util.ArrayList getAllNetNamesSimple(EdifNet net, NetHierarchy netHier, boolean includeTop)
           
static java.util.ArrayList getAllPortNames(EdifNet net, InstanceHierarchy hier, NetHierarchy netHier, boolean includeTop)
           
static EdifNet getInnerMostNet(EdifNet net)
           
 java.util.Map getNameObjectMap()
           
 java.util.ArrayList getOutputPortInstances(NetHierarchy netHier, InstanceHierarchy hier, boolean includeTop)
           
static java.util.List getXilinxNameSuffix(EdifCellInstance cellinst)
          For some cell instances Xilinx adds one or more extensions to the "Logic" name TODO: Describe each rule in more detail.
static boolean isRTObject(EdifNet net)
          Xilinx adds a "_rt" extension to some signals.
static boolean isRTObject(byucc.jhdl.base.Wire wire)
           
static boolean isWSGENObject(EdifNet net)
          Xilinx adds a ".WSGEN" extension to some signals.
static java.io.PrintWriter openWriteFile(java.lang.String fileName)
          This is a helper method to reduce redundant and cluttered code.
static EdifCellInstance parseCell(java.lang.String fileName)
          simply returns the EdifEnvironment from the EDIF file name
 void printMapNames()
          This method prints the signal names parsed from the EDIF file
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait
 

Field Detail

_nameObjectMap

protected java.util.Map _nameObjectMap
This is the main Map of the object. The key is a hierarchical Edif String name and the value is an EdifObject (EdifNet or EdifCellInstance). This is a one to one mapping.


_innerNetsMapCache

protected java.util.Map _innerNetsMapCache

_topInstHier

protected InstanceHierarchy _topInstHier
Constructor Detail

Edif2XilinxName

public Edif2XilinxName(java.lang.String fileName)
Parameters:
fileName - - the name of the EDIF file to parse

Edif2XilinxName

public Edif2XilinxName(EdifCellInstance top)

Edif2XilinxName

public Edif2XilinxName(InstanceHierarchy hier)
Method Detail

createSignalMap

public void createSignalMap(InstanceHierarchy hier)
Parameters:
hier -

createLogicMap

public void createLogicMap(InstanceHierarchy hier)

getInnerMostNet

public static EdifNet getInnerMostNet(EdifNet net)

drivesTopLevelOutputPort

public boolean drivesTopLevelOutputPort(NetHierarchy netHier)

getAllJHDLNetNames

public java.util.ArrayList getAllJHDLNetNames(NetHierarchy netHier,
                                              boolean includeTop)

getAllNetNames

public static java.util.ArrayList getAllNetNames(EdifNet net,
                                                 InstanceHierarchy hier,
                                                 NetHierarchy netHier,
                                                 boolean includeTop)

getAllEdifNetNames

public static java.util.ArrayList getAllEdifNetNames(EdifNet net,
                                                     InstanceHierarchy hier,
                                                     NetHierarchy netHier,
                                                     boolean includeTop)

getAllNetNamesSimple

public static java.util.ArrayList getAllNetNamesSimple(EdifNet net,
                                                       NetHierarchy netHier,
                                                       boolean includeTop)

getAllPortNames

public static java.util.ArrayList getAllPortNames(EdifNet net,
                                                  InstanceHierarchy hier,
                                                  NetHierarchy netHier,
                                                  boolean includeTop)

getOutputPortInstances

public java.util.ArrayList getOutputPortInstances(NetHierarchy netHier,
                                                  InstanceHierarchy hier,
                                                  boolean includeTop)

getNameObjectMap

public java.util.Map getNameObjectMap()

getXilinxNameSuffix

public static java.util.List getXilinxNameSuffix(EdifCellInstance cellinst)
For some cell instances Xilinx adds one or more extensions to the "Logic" name TODO: Describe each rule in more detail.

Parameters:
cellinst -
Returns:

isRTObject

public static boolean isRTObject(EdifNet net)
Xilinx adds a "_rt" extension to some signals. This method attempts to determine if the current net requires this extension. This extension seems to be applied to signals which are within a CLB.

Parameters:
net -
Returns:

isRTObject

public static boolean isRTObject(byucc.jhdl.base.Wire wire)

isWSGENObject

public static boolean isWSGENObject(EdifNet net)
Xilinx adds a ".WSGEN" extension to some signals. This method attempts to determine if the current net requires this extension. The majority of the signals that have this extension added are nets which are driven by by a bus member, or are nets which only drive bus members.

Parameters:
net -
Returns:

openWriteFile

public static java.io.PrintWriter openWriteFile(java.lang.String fileName)
This is a helper method to reduce redundant and cluttered code.

Parameters:
fileName -
Returns:

parseCell

public static EdifCellInstance parseCell(java.lang.String fileName)
simply returns the EdifEnvironment from the EDIF file name

Parameters:
fileName -
Returns:

printMapNames

public void printMapNames()
This method prints the signal names parsed from the EDIF file

Parameters:
names -