Package edu.byu.ece.edif.arch.xilinx

Parses the Xilinx unisim_VCOMP.vhd file, and generates an EdifLibrary containing Xilinx primitive cells.

See:
Description

Class Summary

Edif2XilinxName	This class is used for converting hierarchical EDIF names into valid flattened Xilinx names.
EdifXPowerCompare
EdifXPowerParser
InstanceHierarchy	This class represents an EdifCellInstance object within a hierarchy framework.
InstanceHierarchyIterator	This is an iterator class for the InstanceHierarchy object.
JHDL2XilinxNameMap	This class creates a Map object where the key of the Map is a JHDL Wire object.
NetHierarchy
XilinxGenLib	This class is auto-generated - do not modify
XilinxLibrary	This class will create a Xilinx primitive library.
XilinxMacros	Inserts EdifCell primitives into the Xilinx Library that aren't already in the unisim_VCOMP.vhd file.
XilinxMergeParser	This is a simple class that contains a static method for parsing and merging EDIF files using the Xilinx library as the primitive library.
XilinxTools

Package edu.byu.ece.edif.arch.xilinx Description

Parses the Xilinx unisim_VCOMP.vhd file, and generates an EdifLibrary containing Xilinx primitive cells.

Related Links

• Xilinx Home Page
• Definition of Primitive
• VHDL-AMS Parser in JAVA

Package To Dos