Package edu.byu.ece.edif.tools.sterilize.lutreplace.logicLutRam.RAM.test

Class Summary
allramtest Instances all logic RAMs - to be used to create a LUTRAM replacement library.
jhdllogicramtest Instances all logic RAMs that can be directly implemented in JHDL.
jhdlmultiramtest Instances all JHDL RAMs.
jhdlramtest Instances all JHDL RAMs.
jhdlsimpletest Instances a logic and a JHDL RAMX1D.
jhdlsimpletests Instances a logic and a JHDL RAMX1S.
tb_jhdlRAM Testbench used to compare logic RAM implementation with JHDL Xilinx RAM primitives.
tb_jhdlsimple Testbench used to compare a single logic implementation of a RAMX1D with a single Xilinx RAMX1D primitive.
tb_jhdlsimples Testbench used to compare a single logic implementation of a RAMX1S with a single Xilinx RAMX1S primitive.