edu.byu.ece.edif.tools.sterilize.lutreplace.logicLutRam.RAM.test
Class tb_jhdlRAM

java.lang.Object
  extended by byucc.jhdl.base.Nameable
      extended by byucc.jhdl.base.Node
          extended by byucc.jhdl.base.Cell
              extended by byucc.jhdl.base.Structural
                  extended by byucc.jhdl.Logic.LogicGates
                      extended by byucc.jhdl.Logic.LogicStatic
                          extended by byucc.jhdl.Logic.Logic
                              extended by edu.byu.ece.edif.tools.sterilize.lutreplace.logicLutRam.RAM.test.tb_jhdlRAM
All Implemented Interfaces:
byucc.jhdl.base.BooleanFlags, byucc.jhdl.base.Clockable, byucc.jhdl.base.list.TreeListable, byucc.jhdl.base.TestBench

public class tb_jhdlRAM
extends byucc.jhdl.Logic.Logic
implements byucc.jhdl.base.TestBench

Testbench used to compare logic RAM implementation with JHDL Xilinx RAM primitives.

Version:
$Id:tb_jhdlRAM.java 198 2008-04-16 21:14:21Z jamesfcarroll $
Author:
Nathan Rollins

Field Summary
(package private) static int _count
           
(package private) static int _indata
           
(package private) static int _o128x1s1jhdl
           
(package private) static int _o128x1s1logic
           
(package private) static int _o128x1sjhdl
           
(package private) static int _o128x1slogic
           
(package private) static int _o16x1d1jhdl
           
(package private) static int _o16x1d1logic
           
(package private) static int _o16x1djhdl
           
(package private) static int _o16x1dlogic
           
(package private) static int _o16x1s1jhdl
           
(package private) static int _o16x1s1logic
           
(package private) static int _o16x1sjhdl
           
(package private) static int _o16x1slogic
           
(package private) static int _o32x1d1jhdl
           
(package private) static int _o32x1d1logic
           
(package private) static int _o32x1djhdl
           
(package private) static int _o32x1dlogic
           
(package private) static int _o32x1s1jhdl
           
(package private) static int _o32x1s1logic
           
(package private) static int _o32x1sjhdl
           
(package private) static int _o32x1slogic
           
(package private) static int _o64x1d1jhdl
           
(package private) static int _o64x1d1logic
           
(package private) static int _o64x1djhdl
           
(package private) static int _o64x1dlogic
           
(package private) static int _o64x1s1jhdl
           
(package private) static int _o64x1s1logic
           
(package private) static int _o64x1sjhdl
           
(package private) static int _o64x1slogic
           
(package private) static int _o64x2sjhdl
           
(package private) static int _o64x2slogic
           
(package private) static java.io.PrintStream _outfile
           
(package private) static int _ra
           
(package private) static java.util.Random _rand
           
(package private) static int _wa
           
(package private) static int _we
           
(package private)  byucc.jhdl.base.Wire clk
           
(package private)  byucc.jhdl.base.Wire indatajhdl
           
(package private)  byucc.jhdl.base.Wire indatalogic
           
(package private)  byucc.jhdl.base.Wire o128x1s1jhdl
           
(package private)  byucc.jhdl.base.Wire o128x1s1logic
           
(package private)  byucc.jhdl.base.Wire o128x1sjhdl
           
(package private)  byucc.jhdl.base.Wire o128x1slogic
           
(package private)  byucc.jhdl.base.Wire o16x1d1jhdl
           
(package private)  byucc.jhdl.base.Wire o16x1d1logic
           
(package private)  byucc.jhdl.base.Wire o16x1djhdl
           
(package private)  byucc.jhdl.base.Wire o16x1dlogic
           
(package private)  byucc.jhdl.base.Wire o16x1s1jhdl
           
(package private)  byucc.jhdl.base.Wire o16x1s1logic
           
(package private)  byucc.jhdl.base.Wire o16x1sjhdl
           
(package private)  byucc.jhdl.base.Wire o16x1slogic
           
(package private)  byucc.jhdl.base.Wire o32x1d1jhdl
           
(package private)  byucc.jhdl.base.Wire o32x1d1logic
           
(package private)  byucc.jhdl.base.Wire o32x1djhdl
           
(package private)  byucc.jhdl.base.Wire o32x1dlogic
           
(package private)  byucc.jhdl.base.Wire o32x1s1jhdl
           
(package private)  byucc.jhdl.base.Wire o32x1s1logic
           
(package private)  byucc.jhdl.base.Wire o32x1sjhdl
           
(package private)  byucc.jhdl.base.Wire o32x1slogic
           
(package private)  byucc.jhdl.base.Wire o64x1d1jhdl
           
(package private)  byucc.jhdl.base.Wire o64x1d1logic
           
(package private)  byucc.jhdl.base.Wire o64x1djhdl
           
(package private)  byucc.jhdl.base.Wire o64x1dlogic
           
(package private)  byucc.jhdl.base.Wire o64x1s1jhdl
           
(package private)  byucc.jhdl.base.Wire o64x1s1logic
           
(package private)  byucc.jhdl.base.Wire o64x1sjhdl
           
(package private)  byucc.jhdl.base.Wire o64x1slogic
           
(package private)  byucc.jhdl.base.Wire o64x2sjhdl
           
(package private)  byucc.jhdl.base.Wire o64x2slogic
           
(package private)  byucc.jhdl.base.Wire rajhdl
           
(package private)  byucc.jhdl.base.Wire ralogic
           
(package private)  byucc.jhdl.base.Wire wajhdl
           
(package private)  byucc.jhdl.base.Wire walogic
           
(package private)  byucc.jhdl.base.Wire wejhdl
           
(package private)  byucc.jhdl.base.Wire welogic
           
 
Fields inherited from class byucc.jhdl.Logic.Logic
ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF
 
Fields inherited from class byucc.jhdl.Logic.LogicGates
tech_mapper
 
Fields inherited from class byucc.jhdl.base.Cell
BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD
 
Fields inherited from interface byucc.jhdl.base.BooleanFlags
ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE
 
Constructor Summary
tb_jhdlRAM(byucc.jhdl.base.Node parent)
          Default constructor
 
Method Summary
 void clock()
          functions to be performed on each clock transition
 void getResults()
          grab the integer version of the outputs
 boolean hasBeenTraced()
           
 boolean hasBeenTraced(boolean arg0)
           
 boolean isAsynchronouslyScheduled()
           
 boolean isAsynchronouslyScheduled(boolean arg0)
           
static void main(java.lang.String[] argv)
           
 void reset()
          default startup conditions
 void setInputs()
          drive the inputs of the design
 
Methods inherited from class byucc.jhdl.Logic.Logic
clockDriver, clockDriver, connect_implicit_ports, connectImplicitPorts, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight
 
Methods inherited from class byucc.jhdl.Logic.LogicStatic
add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor
 
Methods inherited from class byucc.jhdl.Logic.LogicGates
add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, or, pulldown, pulldown, pullup, pullup, reg_o, reg_o, reg_o, reg_o, reg, reg, reg, reg, regc_o, regc_o, regc_o, regc_o, regc, regc, regc, regc, regce_o, regce_o, regce_o, regce_o, regce, regce, regce, regce, regp_o, regp_o, regp_o, regp_o, regp, regp, regp, regp, regpe_o, regpe_o, regpe_o, regpe_o, regpe, regpe, regpe, regpe, regr_o, regr_o, regr_o, regr_o, regr, regr, regr, regr, regre_o, regre_o, regre_o, regre_o, regre, regre, regre, regre, regs_o, regs_o, regs_o, regs_o, regs, regs, regs, regs, regse_o, regse_o, regse_o, regse_o, regse, regse, regse, regse, shiftl_o, shiftl, shiftl, shiftr_o, shiftr, shiftr, sub_o, sub_o, sub_o, sub_o, sub_o, sub_o, sub, sub, sub, sub, tbuf_o, tbuf_o, tbuf, tbuf, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor_o, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xnor, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor_o, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor, xor
 
Methods inherited from class byucc.jhdl.base.Structural
behavioralModelIsAvailable, clockMethodIsDisabled, clockMethodIsDisabled, clockMethodIsEnabled, clockMethodIsEnabled, defaultSimulationModelIsBehavioral, hasBehaviorInClockMethod, hasBehaviorInPropagateMethod, isFallingEdgeTriggered, isReadyToBeAsynchronouslyScheduled, isRisingEdgeTriggered, needsToBeAsynchronouslyScheduled, needsToBeClocked, propagate, propagateMethodIsDisabled, propagateMethodIsDisabled, propagateMethodIsEnabled, propagateMethodIsEnabled, willUseHWUpdate, willUseHWUpdate
 
Methods inherited from class byucc.jhdl.base.Cell
addPort, addPorts, addProperties, addProperties, addProperty, addProperty, addProperty, addProperty, antecedantIsBehaviorallyModeled, antecedantIsBehaviorallyModeled, bind, bind, bind, bind, cellInterfaceDeterminesUniqueNetlistStructure, clk, connect, connectAllWires, connectOptional, disableAllBehavioralModels, disableBehavioralModel, enableBehavioralModel, getArgument, getAttachedPort, getAttachedWire, getAttachedWireNoException, getCellName, getCellNetlist, getCellNetList, getCellNetlist, getCellNetlist, getDescendents, getFlatNetlist, getFlatNetlistableChildren, getGeneric, getHeight, getNetlistableChildren, getPlacementInfo, getPortProperties, getPortRecord, getPortRecords, getProperties, getProperty, getPropertyValue, getSinkWires, getSourceWires, getUniqueCellName, getWidth, getX, getY, hasBeenTraced, hasBeenTraced, hasPort, hasPorts, in, in, inout, inout, isAsynchronouslyScheduled, isAsynchronouslyScheduled, isAsynchronousSourceSinkResolved, isBehaviorallyModeled, isBehaviorallyModeledBranch, isInput, isLeafCell, isNetlistable, isNetlistable, isNetlistablePort, isNetlistLeaf, isNotNetlistable, isNotNetlistablePort, isNotVisible, isOutput, isPlaceable, isPlaceable, isPlaced, isPlaced, isPlacementLocked, isRoot, isSimulateable, isSimulateable, isSink, isSource, isVisible, isVisible, join, lockPlacement, nc, out, out, param, popHierarchy, port, port, port, postorderCheck, preorderCheck, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchy, pushHierarchyNoImplicitPorts, pushHierarchyNoImplicitPorts, removeAllUnconnectedPorts, removePort, removeProperty, replaceProperty, replaceProperty, resetBehavioralModelsToDefaults, setAsynchronousSourceSinkResolved, setGeneric, setHeight, setNotNetlistable, setNotNetlistable, setNotVisible, setNotVisible, setPlacementInfo, setPortNotNetlistable, setPortNotNetlistable, setProperty, setWidth, subClassDelete, toString, uniquifyCell, userDefinedClockCount, verifyAndCleanup
 
Methods inherited from class byucc.jhdl.base.Node
addObservable, addSimulatorCallback, checkAll, delete, getBuildingFlag, getChildren, getChildrenEnumeration, getInstanceName, getParent, getParentCell, getRelatives, getSystem, getWires, optimize, orphanAllowed, printAllChildren, printTree, removeSimulatorCallback, setDefaultClock
 
Methods inherited from class byucc.jhdl.base.Nameable
caseSensitivity, caseSensitivity, disableNameClashChecking, getFullName, getFullNameNoTestBench, getHierNameNoTestBench, getInstanceNo, getInstanceNumber, getLeafName, getLeafName, getRelativeName, getUserName, getUserName, hasUserSpecifiedName, isDescendantOf, setInstanceNumber
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait
 

Field Detail

_count

static int _count

_indata

static int _indata

_ra

static int _ra

_wa

static int _wa

_we

static int _we

_o16x1djhdl

static int _o16x1djhdl

_o16x1d1jhdl

static int _o16x1d1jhdl

_o16x1sjhdl

static int _o16x1sjhdl

_o16x1s1jhdl

static int _o16x1s1jhdl

_o32x1djhdl

static int _o32x1djhdl

_o32x1d1jhdl

static int _o32x1d1jhdl

_o32x1sjhdl

static int _o32x1sjhdl

_o32x1s1jhdl

static int _o32x1s1jhdl

_o64x1djhdl

static int _o64x1djhdl

_o64x1d1jhdl

static int _o64x1d1jhdl

_o64x1sjhdl

static int _o64x1sjhdl

_o64x1s1jhdl

static int _o64x1s1jhdl

_o64x2sjhdl

static int _o64x2sjhdl

_o128x1sjhdl

static int _o128x1sjhdl

_o128x1s1jhdl

static int _o128x1s1jhdl

_o16x1dlogic

static int _o16x1dlogic

_o16x1d1logic

static int _o16x1d1logic

_o16x1slogic

static int _o16x1slogic

_o16x1s1logic

static int _o16x1s1logic

_o32x1dlogic

static int _o32x1dlogic

_o32x1d1logic

static int _o32x1d1logic

_o32x1slogic

static int _o32x1slogic

_o32x1s1logic

static int _o32x1s1logic

_o64x1dlogic

static int _o64x1dlogic

_o64x1d1logic

static int _o64x1d1logic

_o64x1slogic

static int _o64x1slogic

_o64x1s1logic

static int _o64x1s1logic

_o64x2slogic

static int _o64x2slogic

_o128x1slogic

static int _o128x1slogic

_o128x1s1logic

static int _o128x1s1logic

_outfile

static java.io.PrintStream _outfile

_rand

static java.util.Random _rand

indatajhdl

byucc.jhdl.base.Wire indatajhdl

wejhdl

byucc.jhdl.base.Wire wejhdl

clk

byucc.jhdl.base.Wire clk

wajhdl

byucc.jhdl.base.Wire wajhdl

rajhdl

byucc.jhdl.base.Wire rajhdl

o16x1djhdl

byucc.jhdl.base.Wire o16x1djhdl

o16x1d1jhdl

byucc.jhdl.base.Wire o16x1d1jhdl

o16x1sjhdl

byucc.jhdl.base.Wire o16x1sjhdl

o16x1s1jhdl

byucc.jhdl.base.Wire o16x1s1jhdl

o32x1djhdl

byucc.jhdl.base.Wire o32x1djhdl

o32x1d1jhdl

byucc.jhdl.base.Wire o32x1d1jhdl

o32x1sjhdl

byucc.jhdl.base.Wire o32x1sjhdl

o32x1s1jhdl

byucc.jhdl.base.Wire o32x1s1jhdl

o64x1djhdl

byucc.jhdl.base.Wire o64x1djhdl

o64x1d1jhdl

byucc.jhdl.base.Wire o64x1d1jhdl

o64x1sjhdl

byucc.jhdl.base.Wire o64x1sjhdl

o64x1s1jhdl

byucc.jhdl.base.Wire o64x1s1jhdl

o64x2sjhdl

byucc.jhdl.base.Wire o64x2sjhdl

o128x1sjhdl

byucc.jhdl.base.Wire o128x1sjhdl

o128x1s1jhdl

byucc.jhdl.base.Wire o128x1s1jhdl

indatalogic

byucc.jhdl.base.Wire indatalogic

welogic

byucc.jhdl.base.Wire welogic

walogic

byucc.jhdl.base.Wire walogic

ralogic

byucc.jhdl.base.Wire ralogic

o16x1dlogic

byucc.jhdl.base.Wire o16x1dlogic

o16x1d1logic

byucc.jhdl.base.Wire o16x1d1logic

o16x1slogic

byucc.jhdl.base.Wire o16x1slogic

o16x1s1logic

byucc.jhdl.base.Wire o16x1s1logic

o32x1dlogic

byucc.jhdl.base.Wire o32x1dlogic

o32x1d1logic

byucc.jhdl.base.Wire o32x1d1logic

o32x1slogic

byucc.jhdl.base.Wire o32x1slogic

o32x1s1logic

byucc.jhdl.base.Wire o32x1s1logic

o64x1dlogic

byucc.jhdl.base.Wire o64x1dlogic

o64x1d1logic

byucc.jhdl.base.Wire o64x1d1logic

o64x1slogic

byucc.jhdl.base.Wire o64x1slogic

o64x1s1logic

byucc.jhdl.base.Wire o64x1s1logic

o64x2slogic

byucc.jhdl.base.Wire o64x2slogic

o128x1slogic

byucc.jhdl.base.Wire o128x1slogic

o128x1s1logic

byucc.jhdl.base.Wire o128x1s1logic
Constructor Detail

tb_jhdlRAM

public tb_jhdlRAM(byucc.jhdl.base.Node parent)
Default constructor

Parameters:
parent - parent node
Method Detail

clock

public void clock()
functions to be performed on each clock transition

Specified by:
clock in interface byucc.jhdl.base.Clockable
Overrides:
clock in class byucc.jhdl.base.Structural

getResults

public void getResults()
grab the integer version of the outputs


reset

public void reset()
default startup conditions

Specified by:
reset in interface byucc.jhdl.base.Clockable
Overrides:
reset in class byucc.jhdl.base.Structural

setInputs

public void setInputs()
drive the inputs of the design


main

public static void main(java.lang.String[] argv)
                 throws java.lang.Exception
Throws:
java.lang.Exception

isAsynchronouslyScheduled

public boolean isAsynchronouslyScheduled()

isAsynchronouslyScheduled

public boolean isAsynchronouslyScheduled(boolean arg0)

hasBeenTraced

public boolean hasBeenTraced()

hasBeenTraced

public boolean hasBeenTraced(boolean arg0)