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Special Notes

The Merge Approach:

  1. Find matching EdifCell Objects
  2. Iterate through all EdifCells in the environment to merge with (from lowest-level)
    1. Modify the EdifCellInstances contained within the EdifCell. If there is structure, modify the structure so that the EdifCellInstances contained by the EdifCell refer to EdifCells that belong in the target library
    2. Insert cell into target library manager
      1. See if a matching cell exists
      2. If passed in cell is structural and target cell is a leaf cell, delete the existing cell and add the passed in cell to the appropriate library and update references to this cell
      3. If there is structure in both, make sure they are the same before adding
    3. If there is no matching Cell in the target library, add cell to library

Supported Invalid EDIF (made good by the EDIF and JHDL packages):

  • If the cell interfaces of a cell merged into the main file doesn't match because one of the port interfaces has expanded buses, while the other one only has buses, or vice versa, then one of the cell interfaces will be expanded or contracted to match the interface of the other, and the port refs of the updated cell will be modified accordingly
  • While merging, if one of the cell interfaces has a multi-bit port, and the other cell interface has a bunch of single-bit ports that correspond to the multi-bit port, and one of the single-bit port's direction doesn't match that of the bus then the expanded interface will be used, and the direction(s) that don't match with the bus will remain
  • If top level cell doesn't match the name of its own file then it gets renamed to match
  • In simulation, a RAMB4 gets repackaged as a RAMB16 when using Virtex2 and gnd gets tied to the unused address bits

Supported EDIF Constructs (not hardcoded, but imported from the EDIF file):

  • Basic essential circuit specific constructs:
    • cell (EdifCell)
    • design (EdifDesign)
    • edif (EdifEnvironment)
    • instance (EdifCellInstance)
    • interface (EdifCellInterface)
    • library (EdifLibrary)
    • net (EdifNet)
    • port (EdifPort)
    • portref (EdifPortRef)
  • Properties for cell, design, edif, instance, library, net, and port
  • Full support for the INIT and INIT_XX properties for instances of: block rams, flip flops, luts, rams, and roms

This work has been sponsored by the NASA AIST program under subcontract to USC-ISI East.
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