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Power Studies

JPower and XPower Callibration

Two basic designs are used to compare the results from JPower and XPower. The first is a simple incrementer and the second design is a loadable counter:

Both the incrementer and loadable counter above can easily fit within a single slice of a CLB. Clearly these two circuits alone consume almost no power. In order to obtain significant power measurement results from JPower and XPower, these circuits are replicated a large number of times. Also, to ensure that the nets of a multibit counter remain relatively active, we restict the bitwidth of the incrementers and counters to be 8 bits wide.

Unfortunately, all of the replicated incrementers are optimized away by the Xilinx tools unless their outputs connect to an IOB. This means that the incrementer can only be replicated as many times as our I/O allows. Since we are using the SLAAC-1V board, our I/O is even further limited. Our outputs go out on the PE1 'Left' channel, and so since the 'Left' channel is 72 bits wide, we can replicate the incrementer 72 times.

To enable us to replicate the incrementer more than just 72 times, we create a second type of replicated incrementer design where groups of incrementer outputs are XOR'ed together. The outputs of these XOR gates are then outputted to IOBs. By adding these XOR gates, we ensure that the incrementers are not optimized away. We now have two different incrementer designs to perform power tests on - a replicated incrementer with each output leading to an IOB, and a replicated incrementer with groups of outputs XOR'ed together.

Loadable Counter
The loadable counter does not have the same problem that the incrementer does. The output of one counter can be fed into the loadable input of another counter - this will ensure that the counters are not optimized away. Therefore we can create a large chain of counters with the final counter's outputs leading to IOBs. Rather than being I/O limited, the replicated counter design is routing resource limited.

TMR Studies
The purpose of calibrating the two different current measuring tools is to help in LANL's TMR studies. More specifically, LANL wants to measure the power costs of TMR. Consequently, previous TMR study results are used with the replicated incrementer and counter designs. Power measurements are taken on all three of the above designs (the two replicated incrementer designs and the replicated counter design) with and without the use of TMR. Previous TMR studies show that a single-bit incrementer along with a single-bit voter cell can fit together in a single slice of a CLB. Thus the voter circuitry does not cost any additional logic. The voter circuitry of the counter however, cannot fit inside existing circuitry and that logic comes at an additional cost to counter triplication.

Clock Triplication
Results of previous LANL TMR tests showed that in order for designs to be immune to single event upsets (SEUs) the clock domain must also be triplicated. In addition to measuring power consumption of non-TMR and TMR versions of the incrementer and counter designs, a separate group of results investigates the incrementer and counter designs with TMR and triplicated clocks.

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