######################################################################
## This Makefile uses the Xilinx tools to create a bitstream
## or other files (IE back-annotation files).
##
## The following variables must be changed according to the design:
##
##    DESIGN - The name of the EDIF design file (without the EDIF extension)
##    PART - The FPGA device to be targetted
##
## The Makefile can be run on the command line to create the following:
##
##    bitfile - type 'make'
##    back annotation files (*.vhd and *.sdf files) - type 'make vhdl'
##    XDL file - type 'make xdl'
######################################################################
NGDBUILD_LOG=ngdbuild.log
PART=v1000fg680-6
TABLE = 1
NGDANNO_OPTIONS = -report
NGD2VHDL_OPTIONS = -w
NGD_OPTIONS=-p $(PART) 
MAP_OPTIONS= -detail -pr o
PAR_OPTIONS=  -pl 5 -rl 1 -w -t $(TABLE)
TRCE_OPTIONS= -a -skew -v 10
XDL_OPTS = -ncd2xdl -nopips
BITGEN_OPTIONS= -w -g StartupClk:Cclk -g readback -g persist:X8 -g DONE_cycle:6

NETLISTJUNK = *.log *.lst *.xpi *.ncd *.par *.bgn *.par *.bit *.bld *.drc *.mrp *.ngo *.ngm *.ngd *.pcf *.dly *.pad *.twr *.mcs *.prm *.x86 *.nav *.rbb *.xdl *.txt *.out *.csv *.nga *.vhd *.sdf *.alf

DESIGN=xp1

all:	${DESIGN}.bit

${DESIGN}.bit : ${DESIGN}.par.ncd
	bitgen ${BITGEN_OPTIONS} ${DESIGN}.par.ncd ${DESIGN}.bit

$(DESIGN).par.ncd : $(DESIGN).ncd
	par $(PAR_OPTIONS) ${DESIGN}.ncd ${DESIGN}.par.ncd

$(DESIGN).ncd : $(DESIGN).ngd
	map $(MAP_OPTIONS) $(DESIGN).ngd -o $(DESIGN).ncd

$(DESIGN).ngd : $(DESIGN).edn
	ngdbuild $(NGD_OPTIONS) $(DESIGN) $(DESIGN).ngd

xdl : ${DESIGN}.par.ncd
	xdl ${XDL_OPTS} ${DESIGN}.par.ncd ${DESIGN}.xdl

twr : ${DESIGN}.par.ncd
	trce ${TRCE_OPTIONS} ${DESIGN}.par.ncd

vhdl : ${DESIGN}.nga
	ngd2vhdl ${NGD2VHDL_OPTIONS} ${DESIGN}.nga

${DESIGN}.nga : ${DESIGN}.par.ncd
	ngdanno -o ${DESIGN}.nga ${DESIGN}.par.ncd ${DESIGN}.ngm

netlistclean:
	rm -f $(NETLISTJUNK)