######################################################################
## This ModelSim *.do file is used on the command-line to create *.vcd
## files, given a *.vhd file and a *.sdf file.
##
## This 'do' file uses Tcl commands.  It is specific to Nathan Rollins'
## TMR counter tests.  This 'do' file ensures that all of the design
## inputs have loads (especially the clocks) and then simulates the
## design for a specified time before outputting a *.vcd file.  The 
## required inputs to the 'do' file are (in this order):
##      [-cnt [-tmr]] [-3clk] <1/2 clk_period (in ns)> <clk_period in (ns)> \
##      <clk_frequency (in MHz)> <simulation_runtime (in us)>
##
## NOTE: The last 4 parameters could be determined with a single input
##       however for flexibility purposes they are 4 separate inputs.
##       The input entitled "1/2 clk_period" determines the duty cycle
##       The input entitled "clk_frequency" is used for a file name
##       The input entitled "simulation_runtime" should be long enough
##       to ensure all the design nets are activated.
######################################################################

vlib work
vcom xp1.vhd
vsim -sdfmax xp1.sdf -t 10ps root

if {${1} == "-cnt"} {
   shift
   if {${1} == "-tmr"} {
      shift
      force root/reset(0) 0
      force root/reset(1) 0
      force root/reset(2) 0
   } else {
      force root/reset 0
   }
}

if {${1} == "-tmr"} {
   shift
}

if {${1} == "-3clk"} {
   shift
   force root/clk(0) 0,1 ${1}ns -r ${2}ns
   force root/clk(1) 0,1 ${1}ns -r ${2}ns
   force root/clk(2) 0,1 ${1}ns -r ${2}ns
} else {
   force root/clk 0,1 ${1}ns -r ${2}ns
}

vcd file xp1_${3}.vcd
vcd add root/*
run ${4}us
quit -f