XPower is a Xilinx tool which estimates the power consumption of a given placed FPGA design. The design inputted to XPower can either be in the form of a *.par.ncd file or *.ncd and *.pcf files.

In order for XPower to be able to determine the power consumption of a given design, every net in the design must have an activity rate assigned to it. There are three ways in which to specify activity rates for each net:

Regardless of which method is used, XPower can report the confidence level of it's power estimation. When all the nets have activity rates assigned to them, XPower reports an 'accurate' confidence level. If some of the nets do not have activity rates assigned, the confidence level is reported as 'reasonable', and if a significant number of nets do not have an activity rate assigned to them, XPower reports an 'inaccurate' confidence level. Whichever method is used to assign activity rates to a design's nets, an 'accurate' XPower confidence level is important.

XPower can create XML files as a means of saving session settings. An XPower-created XML file can be loaded to restore a previous XPower session. A JHDL program can be used to determine the activity rates of the nets from a given design, and then use that information to create an XML file that is readable by XPower. An example of such a JHDL class is given below. This example is specific to Nathan Rollins' TMR counter tests, but can easily be modified for any design:

Creating XML files using JHDL successfully assigns activity rates to every net of a design (and acheive an 'accurate' confidence level in XPower), however JHDL is unable to simulate transient signals. Without being able to simulate transient signals, the activity rates produced by JHDL will be too low resulting in inaccurate XPower power consumption reports. Due to the inaccuracy in this method, back-annotation was investigated as a method importing net activity rate information.

ModelSim can be used to create a *.vcd file needed by XPower to import net activity rates. The Xilinx tools can be used to create the back annotated files needed by ModelSim. An important difference between the back annotation method and the XPower XML method of importing net activity rate information is that net timing information can be back annotated with the Xilinx tools. This timing information will take into account transient signals in the design (information that is lacking in the XPower XML method). The following makefile can be used to generate back annotated files, given an EDIF file:

Once the back annotated files have been created, ModelSim can be used to generate the *.vcd files needed by XPower. Unfortunately, the net names in the *.vcd files created by ModelSim are not in the format required by XPower. Thus, a Perl script is used to fix the net names in the *.vcd files. ModelSim can be run in commandline mode and can also import commands in script files called 'do' files. An example of how *.vcd files can be created and corrected using ModelSim and two Perl scripts is given below. These files were used for Nathan Rollins' TMR counter tests:

Once The *.vcd files have been created and the net names have been 'fixed', they can be imported into XPower. XPower will then estimate the power consumption of the design. Below is a Perl script that uses a command-line version of XPower to find the current used in a design run at a range of different frequencies: