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36-bit Counter

Specifications
  • Iterations: 5810024
  • Clock frequency: 10 MHz
  • Freerunning clock
  • Sequential corruption
  • Persistence wait time: 1000 u seconds
  • Persistence error window: 50 cycles
Results
  • Sensitivity test error rate: 5170 / 5810024 = %0.0889841
  • Persistence test error rate: 511 / 5810024 = %0.00879514
  • Total test time: 1263 seconds
  • 0.000217383 seconds per iteration

Figure 1a: Physical Placement of Sensitive Configuration Bits in 36-bit Counter


Figure 1b: Physical Placement of Persistent Configuration Bits in 36-bit Counter


Figure 2a: Detail of Physical Placement of Sensitive Configuration Bits in 36-bit Counter


Figure 2b: Detail of Physical Placement of Persistent Configuration Bits in 36-bit Counter
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