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Simulation Results

Overview
The SEU Simulator developed at BYU finds and records both sensitive and persistent configuration bits in an FPGA. The following are simulation results of selected designs. Graphics show the relative physical placement of sensitive (or persistent) configuration bits in the FPGA. Brighter color indicates higher sensitivity (or persistence).

Selected Designs
Definitions
  • Iterations: The number of times any bit was upset in the configuration bitstream.
  • Clock frequency: The frequency at which the fpga is clocked.
  • Freerunning clock: The clock freeruns during times the simulator is allowing the circuit to operate.
  • Stepped clock: The clock is controlled by the simulator during time the simulator is allowing the circuit to operate. The simulator issues a number of 'step' commands to clock the circuit.
  • Sequential corruption: The simulator upset the configuration bits in a sequential pattern. This method allows for more controlled, repeatable tests.
  • Random corruption: The simulator randomly selects configuration bits to upset. This method more closely resembles the randomness of configuration bit upsets in high energy fields such as outer space.
  • Persistence wait time: When an output error is detected the simulator fixes the configuration bit and then runs the cirucit for an additional amount of user defined time, 'persistence wait time', to see if the error flushes out of the system.
  • Persistence error window: At the end of 'persistence wait time' (see above) the simulator checks if an output error occured within the last 'z' cycles. This user specified parameter is defined as the persistence error window. If the output is in error, the simulator marks the most recently upset configuration bit as 'persistent'.
  • Persistent: A configuration bit is deemed 'persistent' if, after the configuration bit is fixed, the circuit does not recover. To recover a circuit must flush out any output errors within 'persistence wait time' (see above).
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