BYU Home page BRIGHAM YOUNG UNIVERSITY
Department Title
Navigation Menu


Design Tutorial

Overview
This tutorial goes through the steps to create a simple digital design, synthesize the design to create a Placed and Routed .ncd file and finally create two distinct .bit files which can be used in the BYU SEU simulator.

Steps
  1. Create the .EDF file
    • Use this VHDL file or recreate the design.
    • This is the design:
      • Figure 1:
      • A thirty-six bit adder with the result registered. (XP_IN[71:36] + XP_IN[35:0])
      • A thirty-six bit subtractor with the result registered. (XP_IN[71:36] - XP_IN[35:0])
      • A concatenator which takes the registered adder output and concatenates it to the registered subtractor output. The output of the concatenator is registered.
      • The input port must be named XP_IN[71:0]
      • The output port must be named XP_OUT[71:0]
      • The clock port must be named XP_PCLK
      • The reset port must be named XP_RST
      • Buffer XP_PCLK with an IBUFG followed by a BUFG
      • Buffer XP_RST with an IBUFG, latch it in a flip-flop and buffer it through a BUFG
        • A special constraint must be included in each .ucf file:
              INST "RST_BUFG" LOC = GCLKBUF0;
          where RST_BUFG is the instance name of XP_RST's BUFG
      • Do not have any other ports.
    • Name the file xp_tutorial.vhd
    • Use a synthesis tool to create a .edf file. Name it xp_tutorial.edf
  2. Synthesize the design
  3. Convert the .ncd files for xp1 to .xdl format
    • Before the SEU simulation tests can be performed, half-latches must be removed from the design to be placed in xp1.
    • BYU will remove the half-latches, but the required file format is .xdl
    • To convert the Placed and Routed .ncd file for xp1 to .xdl format use the xdl tool. At the command line type: xdl -ncd2xdl xp1.par.ncd xp1.xdl
  4. Use the RadDRC tool (only available on cougar) to remove half-latches from the .xdl file
  5. Convert the fixed .xdl file back to .ncd format
    • At the command line type: xdl -xdl2ncd xp1-fixed.xdl xp1-fixed.ncd
  6. Place and Route the fixed .ncd file
    • The half-latch removal process disrupts the placement and routing.
    • Use PAR to Place and Route the xp1-fixed.ncd file: par -w xp1-fixed.ncd xp1-fixed.par.ncd
  7. Create the Bit Files
    • Set these environment variables
      • XVKMA_CORE_LUT_PACK=TRUE
      • GUIDE_NEW=TRUE
    • Repeat the following step in both the xp1 and xp2 directories to create a .bit file for both xp1 and xp2 (using the Xilinx XST 5.1, 7.1sp4, or 8.x tools tools) (replacing xp1-fixed with xp2 when in the xp2 directory)
      1. bitgen -w -g StartupClk:Cclk -g readback -g persist:X8 -l -m -g DONE_cycle:6 xp1-fixed.par.ncd xp1-fixed.bit
  8. Run the design through the SEU Simulator (The BYU-LANL Fault injection Tool)
    • The operation of the SEU Simulator is described here.
Simulation Results
  • This is the output results file for the xp_tutorial design. The first section is an overview of the results, including the error rate. Since this is a relatively small design there are only about 800 errors detected. The next section is an array which consists of approximately six million numbers which represent the number of errors for each and every configuration bit. The final section is another array which represents the number of times the simulator injected a fault into each of the approximately six million configuration bits.
  • Open up this file in Matlab to get a graphical representation of the error rate.
    • The following are commands to give Matlab to create the graphic:
      1. load -ascii < output file name > .txt;
      2. failures = < output file name > (1:4778,:)';
        (Do not include the file extension)
      3. tested = < output file name > (4779:end,:)';
      4. probability = failures/tested;
      5. imagesc(variable)
        (*Where variable equals either the failures, tested or probability variables)
  • This is an example of the graphic file Matlab will produce.

    (This is not a graphic of xp_tutorial. That design is so small that the graphic does not show any red dots.) This particular graphic is of the failures variable for a different design. The brightness of the red dot indicates the relative number of errors which occured at that bit location
Related Links