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Legacy SLAAC1-V X0 Design Creation Howto


Overview

The objective of this tutorial is to document the procedures necessary for creating a VHDL X0 design for use with the legacy SLAAC1-V distribution. Since the time of writing of the documentation included with the legacy SLAAC1-V distribution, a few things have changed with Synplicity, requiring a few minor, but very necessary, changes.

Steps
  1. Create the X0 VHDL code
    • Use the following VHDL file as a template: x0.vhd
  2. Netlist the X0 design
    • Run the following synplify project file in batch mode: x0_batch.prj
      • Modify the variables inside the project file, SLAAC_ROOT and SYNPLIFY_ROOT
      • add any additional VHDL files you may have, after the line which says add_file -vhdl -lib "x0.vhd"
      • run either synplify -batch x0_batch.prj or synplify_pro -batch x0_batch.prj
  3. Synthesize the X0 design
    • Download this ucf file to your working directory: slaac1v_ifx0.ucf
    • With the Xilinx ISE tools installed, you should be able to run this makefile (tested only under Linux with the 6.1 tools)
      • Rename the file to makefile
      • Modify the variables inside the makefile, SLAAC_ROOT and SYNPLIFY
      • Run the command make
      • Verify that the file x0.par indicates that 100% of the External IOBs have been LOCed - if not, something has gone wrong, and you should NOT download the bitstream to the SLAAC1-V board.
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