Overview

While configurable systems have been shown to be very effective for high-throughput sensor processing, they are relatively unsuitable for operation in the hostile space environment. Like dense memory arrays, FPGAs are susceptible to temporary upsets in the state of its internal memory cells. Such upsets destroy not only the internal data used by the FPGA, but configuration information used to determine the circuitry performed by the FPGA. In order for FPGAs to be used reliably in a space environment, methods must be identified to detect and correct transient memory upsets. Further, design methods must be created to improve the reliability and robustness of FPGA designs operating under these conditions. This effort will investigate methods for improving the reliability of FPGA designs operating in a space environment by creating a testbed for automatically testing the reliability of FPGA designs, investigating specific FPGA bitstream issues related to reliability and identifying design techniques to improve the reliability of FPGA designs.

Director

Projects

Soft Processor & Fault Injection

• Michael Gardiner, Jae Lee, Luke Hsiao, Nathan Harward

BYU Object Avoidance

• Alex Wilson, Matthew Bohman, Luke Newmeyer, Alex Lin, Kyle Davidson

CHREC Space Processor & Scrubbing

• Aaron Stoddard, Ammon Gruwell, Alex Wilson

Multi-Gigabit Transceiver

• Alex Harding, Matthew Cannon